Si5317D数据手册集成电路（IC）的时钟发生器PLL频率合成器规格书PDF

描述 Description

The Si5317D jitter attenuator combines third-generation DSPLL technology to enable any-frequency clock generation and jitter attenuation for applications requiring a high level of jitter performance. This device supports 1 input(s), 2 output(s) and has a maximum frequency output of 100 MHz. The Si5317D delivers 0.3 ps rms phase jitter performance with 0 ppm error. The loop filter is fully integrated on-chip, eliminating the risk of noise coupling associated with discrete solutions. Further, the jitter attenuation bandwidth is digitally programmable, providing jitter performance optimization at the application level.

简介

Si5317D属于集成电路（IC）的时钟发生器PLL频率合成器。由制造生产的Si5317D时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。