SE555-SP中文资料QML V 类精密计时器数据手册TI规格书

描述 Description

The SE555 is a precision timing circuit capable of producing accurate time delays or oscillation. In the time-delay or monostable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground. The output circuit is capable of sinking or sourcing current up to 100 mA. Operation is specified for supplies of 4.5 V to 16.5 V. With a 5-V supply, output levels are compatible with TTL inputs.

特性 Features

• Timing From Microseconds to Hours
• Adjustable Duty Cycle
• QML-V Qualified, SMD 5962-98555
• Rad-Tolerant: 25 kRad (Si) TID

Radiation tolerance is a typical value based upon initial device qualification with dose rate = 10 mrad/sec. Radiation Lot Acceptance Testing is available - contact factory for details.