SDN06464D1BJ1SA-60IR中文资料ETC数据手册PDF规格书

Features:

 200-pin 64-bit DDR1 Small Outline Dual-In-Line Double

Data Rate Synchronous DRAM module

 Module organization: single rank 64M x 64

 VDD = 2.5V ±0.2V, VDDQ 2.5V ±0.2V

 VDD = 2.6V ±0.1V, VDDQ 2.6V ±0.1V (DDR400)

 2.5V I/O ( SSTL_2 compatible)

 Serial Presence Detect with EEPROM

 Gold-contact pads

 This module is fully pin and functional compatible to the

JEDEC PC-3200 spec. and JEDEC- Standard MO-224.

(see www.jedec.org)

 The pcb and all components are manufactured according

to the RoHS compliance specification [EU Directive

2002/95/EC Restriction of Hazardous Substances (RoHS)]

 DDR1 - SDRAM component Samsung K4H510838J

 64Mx8 DDR1 SDRAM in 60-ball FBGA package

 Internal, pipelined double-data-rate (DDR)

 2n pre-fetch architecture

 DLL to align DQ and DQS transitions with CK

 Bidirectional data strobe (DQS) transmitted/received with

data, source-synchronous data capture

 Differential clock inputs (CK and CK#)

 Commands entered on each positive CK edge

 Four internal banks for concurrent operation

 Data mask (DM) for masking write data

 Programmable burst length: 2,4 or 8

 Adjustable data-output drive strength

 Auto Refresh (CBR) and Self Refresh, 8k Refresh every

64ms