SDA9361中文资料DDC-PLUS-Deflection Controll数据手册Infineon规格书

描述 Description

General Description
The SDA 9361 is a highly integrated deflection controller for CTV receivers with standard or doubled line and field frequencies. It controls among others an horizontal driver circuit for a flyback line output stage, a DC coupled vertical saw-tooth output stage and an east/west raster correction circuit. All adjustable output parameters are Ι2C Bus controlled. Inputs are HSYNC and VSYNC. The HSYNC signal is the reference for the internal clock system which includes the Φ1 and Φ2 control loops.

特性 Features

• Deflection - Protection - 16:9 / 4:3
• Φ1 PLL and Φ2 PLL on chip
• All EW-, V- and H- functions
• PH EHT compensation
• Upper/lower EW-corner correction separately adjustable
• V-bow correction: Vertical frequent parabolic modulation of H-phase
• H-frequent PWM output signal for general purpose
• Partial overscan adjustable to hide the cut off control measuring lines in the reducedscan modes
• Control signal SCAN as reference for vertical positioning of OSD, PIP etc.
• Vertical noise reduction with memory
• Self adaptation of V-frequency/number of lines per field between 192 and 680 for each possible line frequency
• Protection against missing V-deflection (CRT-protection)
• Clock generation on chip
• 5 V supply voltage