SC9256S中文资料PLL FOR DTS数据手册Silan规格书

描述 Description

DESCRIPTION
The SC9256 is phase-locked loop (PLL) LSIs for digital tuning systems (DTS) with built in 2 modulus prescalers.
All functions ate controlled through 3 serial bus lines. These LSIs are used to configure high-performance digital tuning system.FEATURES
* Optimal for configuring digital tuning systems in high-fi tuners and car stereos.
* built-in prescalers. Operate at input frequency ranging from 30~150 MHz during FMIN input (with 2 modulus prescaler) and at 0.5~40MHz during AMIN input (with 2 modulus prescaler or direct dividing).
* 16 bit programmable counter, dual parallel output phase comparator, crystal oscillator and reference counter.
* 3.6MHz, 4.5MHz, 7.2MHz or 10.8MHz crystal oscillators can be used.
* 15 possible reference frequencies. ( When using 4.5MHz crystal)
* Built-in 20 bit general-purpose counter for such uses as measuring intermediate frequencies (IFIN1 and IFIN2)
* High-precision (±0.55~±7.15µs) PLL phase error detection.
* Numerous general-purpose I/O pins for such uses as peripheral circuit control.
* 3 N-channel open-drain output ports (OFF withstanding voltage:12V) for such uses as control signal output.
* Standby mode function (turns off FM, AM and IF amps) to save current consumption.
* All functions controlled through 3 serial bus lines.
* CMOS structure with operating power supply range of VDD=5.0±0.5V.

特性 Features

* Optimal for configuring digital tuning systems in high-fi tuners and car stereos.
* built-in prescalers. Operate at input frequency ranging from 30~150 MHz during FMIN input (with 2 modulus prescaler) and at 0.5~40MHz during AMIN input (with 2 modulus prescaler or direct dividing).
* 16 bit programmable counter, dual parallel output phase comparator, crystal oscillator and reference counter.
* 3.6MHz, 4.5MHz, 7.2MHz or 10.8MHz crystal oscillators can be used.
* 15 possible reference frequencies. ( When using 4.5MHz crystal)
* Built-in 20 bit general-purpose counter for such uses as measuring intermediate frequencies (IFIN1 and IFIN2)
* High-precision (±0.55~±7.15µs) PLL phase error detection.
* Numerous general-purpose I/O pins for such uses as peripheral circuit control.
* 3 N-channel open-drain output ports (OFF withstanding voltage:12V) for such uses as control signal output.
* Standby mode function (turns off FM, AM and IF amps) to save current consumption.
* All functions controlled through 3 serial bus lines.
* CMOS structure with operating power supply range of VDD=5.0±0.5V.