SC68C652BIB48数据手册恩XP中文资料规格书

描述 Description

OverviewThe SC68C652B is a 2 channel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s. The SC68C652B is pin compatible with the SC68C2550B. The SC68C652B provides enhanced UART functions with 32-byte FIFOs, modem control interface, DMA mode data transfer, and infrared (IrDA) encoder/decoder. The DMA mode data transfer is controlled by the FIFO trigger levels and the TXRDY and RXRDY signals. On-board status registers provide the user with error indications and operational status. System interrupts and modem control features may be tailored by software to meet specific user requirements. An internal loop-back capability allows on-board diagnostics. Independent programmable baud rate generators are provided to select transmit and receive baud rates.
The SC68C652B operates at 5 V, 3.3 V and 2.5 V and the industrial temperature range, and is available in the plastic LQFP48 package.

特性 Features

•2 channel UART with Motorola® uP interface

•5 V, 3.3 V and 2.5 V operation

•5 V tolerant inputs

•Industrial temperature range (-40 Cel to +85 Cel)

•Software compatible with industry standard 16C450, 16C550, and SC16C650

•Up to 5 Mbit/s baud rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V

•32-byte transmit FIFO to reduce the bandwidth requirement of the external CPU

•32-byte receive FIFO with error flags to reduce the bandwidth requirement of the external CPU

•Independent transmit and receive UART control

•Four selectable receive and transmit FIFO interrupt trigger levels

•Automatic software (Xon/Xoff) and hardware (RTS/CTS) flow control

•Programmable Xon/Xoff characters

•Software selectable baud rate generator

•Standard modem interface or infrared IrDA encoder/decoder interface

•Supports IrDA version 1.0 (up to 115.2 kbit/s)

•Sleep mode

•Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break)

•Transmit, Receive, Line Status, and Data Set interrupts independently controlled

•Fully programmable character formatting:
•5, 6, 7, or 8-bit characters

•Even, odd, or no parity formats

•1, 1 1/2, or 2 stop bit generation

•Baud generation (DC to 5 Mbit/s)




•False start bit detection

•Complete status reporting capabilities

•3-state output TTL drive capabilities for bi-directional data bus and control bus

•Line break generation and detection

•Internal diagnostic capabilities:
•Loop-back controls for communications link fault isolation




•Prioritized interrupt system controls

•Modem control functions (CTS, RTS, DSR, DTR, RI, and CD)