SAM9X60数据手册Microchip中文资料规格书

描述 Description

The SAM9X60 is a high-performance, ultra-low-power ARM926EJ-S CPU-based embedded microprocessor (MPU) running up to 600 MHz. The SAM9X60 supports various memory interfaces, including 16-bit LPDDR/DDR2, 32-bit LPSDR/SDRAM, NAND Flash, Quad SPI and eMMC Flash. The device integrates powerful peripherals for connectivity and user interface applications. It offers State-of-the-Art security functions such as SecureBoot capability with on-chip secure key storage (OTP), high-performance crypto accelerators (SHA, AES and TDES) as well as tamper pins.

Microchip offers for different supply and DRAM configurations, fully tested power management solutions respecting the SAM9X60 power sequencing specifications. Go to Treelinktool under DC/DC converters and SAM9X60 for further information.

特性 Features

High-performance Architecture:
• 600MHz ARM926EJ-S Core, 200MHz System/Memory Bus
• 32 kB Data Cache and 32kB Instruction Cache
Memories:
• 16/32-bit SDR/LPSDR Controller
• 16-bit Multi-port DDR2/LPDDR Controller
• 64 kB internal SRAM
Enhanced User Interface capability:
• 24-bit LCD Controller with overlays up to 1024x768 resolution
• 2D Graphics Engine, Camera Interface
• Built-in Class D Amplifier
Large number of connectivity options:
• Dual 10/100 Ethernet, Dual CAN, Dual SD Card/eMMC
• Two High-speed USB Host + One High-speed Host or Device
• Thirteen FLEXCOMs (USART, SPI and I²C)
State-of-the-Art Security:
• Hardware Encryption Engine (TDES, AES and SHA) and True Random Generator (TRNG)
• Secure Boot with on-chip Secure Key Storage (OTP)
• Physical protection against tamper, 8 tamper detection pins
• On the Fly scrambling / unscrambling for memories
Rich Development Ecosystem:
• Free mainline Linux® Distribution
• MPLAB® X Integrated Development Environment and MPLAB® Harmony v3
• Multiple Third-party Software and Hardware Solutions
Optimized for Easy PCB Design and Low EMI:
• TFBGA228, 11x11, 0.65 mm pitch
• Power/GND balls placed and distributed for optimal decoupling
• Fractional System PLL, I/Os slew rate and drive control, DDR I/Os calibration for Low EMI