SAA7219HS中文资料飞利浦数据手册PDF规格书

GENERAL DESCRIPTION

SAA7219 overview

The device is part of a comprehensive source decoding kit which contains all the hardware and software required to receive and decode MPEG-2 transport streams, including descrambling, demultiplexing. In addition, it includes a PR3930 core which is a 32-bit MIPS RISC-based CPU core supporting the MIPS 16 instruction set to reduce memory requirements and several peripheral interfaces such as UARTs, I2C-bus units, an IEC 1883, and an IEEE 1284 (Centronics) interface. The SAA7219 is therefore capable of performing all controller tasks in digital television receiver applications such as set-top boxes. Furthermore, the SAA7219 is compliant to DVB and MULTI2 standards.

FEATURES

• Conditional access descrambling Digital Video Broadcasting (DVB) compliant and MULTI2 compliant

• Stream demultiplexing: Transport Stream (TS), Packetized Elementary Stream (PES), program and proprietary streams

• Internal 32-bit MIPS RISC based Central Processing Unit (CPU) supporting MIPS16 instruction set and running at 81 MHz

• Low-power sleep modes supported across the chip

• Comprehensive driver software and development tool support

• Package: SQFP208.