SAA7158WP中文资料飞利浦数据手册PDF规格书

GENERAL DESCRIPTION

Application Environment

The Back END IC (abbreviated as BENDIC) is designed to cooperate with an 8051 type of microprocessor, the ECO3 (SAA4951) memory controller and Texas Instruments TMS4C2970 memories, but other configurations may be applicable. Fig.1 shows the block diagram of the feature box. The nominal clock frequency of the IC is 27 MHz or 32 MHz, with a maximum of 36 MHz.

FEATURES

• Line Flicker Reduction (LFR) by means of MEDIAN filtering

• Vertical zoom

• Digital colour transient improvement

• Digital luminance peaking

• Movie phase detection

• 4:4:4 YUV data throughput selectable, standard is 4:1:1 Y/U/V

• D/A conversion

• UART interface.