SAA7157T中文资料飞利浦数据手册PDF规格书

GENERAL DESCRIPTION

The SAA7157 generates all clock signals required for a digital TV system suitable for the SAA715x family and the SAA7199B (DENC). The circuit operates in either the phase-locked loop mode (PLL) or voltage controlled oscillator mode (VCO).

FEATURES

• Clock generation suitable for digital TV systems (line-locked)

• PLL frequency multiplier to generate 4 times of input frequency

• Dividers to generate clocks LL1.5A, LL1.5B, LL3A and LL3B (4th and 2nd multiples of input frequency)

• PLL mode or VCO mode selectable

• Reset control and power fail detection

• Suitable for applications with feature box and picture memory