SAA7120中文资料Digital Video Encoder (ConDENC)数据手册恩XP规格书

描述 Description

GENERAL DESCRIPTION
The SAA7120; SAA7121 encodes digital YUV video data to an NTSC or PAL CVBS or S-Video signal.
The circuit accepts CCIR compatible YUV data with 720 active pixels per line in 4:2:2multiplexed formats, for example MPEG decoded data. It includes a sync/clock generator and on-chip DACs.FEATURES
• Monolithic CMOS 3.3 V (5 V) device
• Digital PAL/NTSC encoder
• System pixel frequency 13.5 MHz
• Accepts MPEG decoded data on 8-bit wide input port; input data format Cb-Y-Cr (CCIR 656), SAV and EAV
• Three DACs for Y, C and CVBS, two times oversampled with 10 bit resolution
• Real time control of subcarrier
• Cross colour reduction filter
• Closed captioning encoding and WST- and NABTS-Teletext encoding including sequencer and filter
• Line 23 wide screen signalling encoding
• Fast I2C-bus control port (400 kHz)
• Encoder can be master or slave
• Programmable horizontal and vertical input synchronization phase
• Programmable horizontal sync output phase
• Internal colour bar generator (CBG)
• 2×2 bytes in lines 20 (NTSC) for copy guard management system can be loaded via I2C-bus
• Down-mode of DACs
• Controlled rise/fall times of synchronization and blanking output signals

特性 Features

• Monolithic CMOS 3.3 V (5 V) device
• Digital PAL/NTSC encoder
• System pixel frequency 13.5 MHz
• Accepts MPEG decoded data on 8-bit wide input port; input data format Cb-Y-Cr (CCIR 656), SAV and EAV
• Three DACs for Y, C and CVBS, two times oversampled with 10 bit resolution
• Real time control of subcarrier
• Cross colour reduction filter
• Closed captioning encoding and WST- and NABTS-Teletext encoding including sequencer and filter
• Line 23 wide screen signalling encoding
• Fast I2C-bus control port (400 kHz)
• Encoder can be master or slave
• Programmable horizontal and vertical input synchronization phase
• Programmable horizontal sync output phase
• Internal colour bar generator (CBG)
• 2×2 bytes in lines 20 (NTSC) for copy guard management system can be loaded via I2C-bus
• Down-mode of DACs
• Controlled rise/fall times of synchronization and blanking output signals