Low-voltage digital IF receiver

DESCRIPTION The SA637 is a low-voltage high performance monolithic digital system with high-speed RSSI incorporating a mixer, oscillator with buffered output, two limiting intermediate frequency amplifiers, fast logarithmic received signal strength indicator (RSSI), voltage regulator, RSSI o

文件：144.3 Kbytes 页数：11 Pages

PHI

PHI

Low-voltage digital IF receiver

DESCRIPTION\nThe SA637 is a low-voltage high performance monolithic digital system with high-speed RSSI incorporating a mixer, oscillator with buffered output, two limiting intermediate frequency amplifiers, fast logarithmic\nreceived signal strength indicator (RSSI), voltage regulator, RSSI op amp •VCC= 2.7 to 5.5V\n•Low power receiver (3.8mA @ 3V)\n•Power down mode (ICC= 110µA)\n•Fast RSSI rise and fall times\n•Extended RSSI range with temperature compensation\n•RSSI op amp\n•2MHz limiter small signal bandwidth\n•455kHz filter matching (1.5kΩ)\n•Differential limiter output\n•Oscillator buffe;

恩XP

Low-voltage digital IF receiver

DESCRIPTION The SA637 is a low-voltage high performance monolithic digital system with high-speed RSSI incorporating a mixer, oscillator with buffered output, two limiting intermediate frequency amplifiers, fast logarithmic received signal strength indicator (RSSI), voltage regulator, RSSI o

文件：144.3 Kbytes 页数：11 Pages

PHI

PHI

TOP LED DEVICE

文件：519.01 Kbytes 页数：11 Pages

SEOUL

首尔半导体

Reconfigurable FPGA with 16 x 16 bit Analog Input

Application Information The TXMC637 is a standard single-width Switched Mezzanine Card (XMC) compatible module providing a user configurable FPGA (AMD Artix™ 7). 32 ADC input channels, based on four ADAS3022, can be software configured in groups to operate in single-ended or differential mod

文件：450.34 Kbytes 页数：3 Pages

TEWS

VDSL FILTER SOLUTIONS

文件：316.54 Kbytes 页数：2 Pages

DELTA

台达电子