S9S08SL16E1V28R中文资料飞思卡尔数据手册PDF规格书

MC9S08EL32 Features

8-Bit HCS08 Central Processor Unit (CPU)

• 40-MHz HCS08 CPU (central processor unit)

• HC08 instruction set with added BGND instruction

• Support for up to 32 interrupt/reset sources

On-Chip Memory

• FLASH read/program/erase over full operating voltage and temperature

• EEPROM in-circuit programmable memory; program and erase while executing FLASH; erase abort

• Random-access memory (RAM)

• Security circuitry to prevent unauthorized access to RAM and NVM contents

Power-Saving Modes

• Two very low-power stop modes

• Reduced power wait mode

• Very low-power real-time interrupt for use in run, wait, and stop

Clock Source Options

• Oscillator (XOSC) — Loop-control Pierce oscillator; Crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz

• Internal clock source (ICS) — Contains a frequency-locked loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2 resolution and 2 deviation over temperature and voltage; supports bus frequencies from 2–20 MHz

System Protection

• Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus clock

• Low-voltage detection with reset or interrupt; selectable trip points

• Illegal opcode detection with reset

• Illegal address detection with reset

• FLASH and EEPROM block protect

Development Support

• Single-wire background debug interface

• Breakpoint capability allows single breakpoint setting during in-circuit debugging (plus two more breakpoints in the on-chip debug module)

• In-circuit emulation (ICE) debug module — contains two comparators and nine trigger modes; eight-deep FIFO for storing change-of-flow address and event-only data; supports both tag and force breakpoints