S5L9250B01-Q0R0中文资料三星数据手册PDF规格书

INTRODUCTION

The CD-ROM 48X 1 chip receives the input signal read from the CD-DA/VIDEO-CD/CD-ROM disc after handling by the RF amplifier. The signal is input into the digital servo block which has a built-in DSP core, and goes through focus and tracking adjustments. The RF signal input into a data path goes through the data slicer, PLL, EFM demodulator, C1/C2 ECC and the audio handling block. In the case of a CD-DA, the signal is output through the 1-bit DAC. In the case of a CD-ROM, the signal is input into an external CD-ROM controller for handling, then transmitted to the host through the ATAPI I/F. Also, if you operate the CD-DA in audio buffering mode while already in CAV mode, the signal is stored in the CD-ROM controller DRAM at high speed, then output at 1x from the CD-ROM controller, after passing through the 1-bit DAC built-in to the S5L9250B.

FEATURES

• Main Features

- Digital servo, CD-DSP, 1-bit DAC.

- 33.8688MHz crystal.

- Supports CLV 4X and 8X.

- Supports CAV MAX 16X, 20X, 24X, 32X, 40X, and 48X.

- Interrupt (SINTB)

- MICOM interface

• Digital Servo Block

- Automatic adjusting feature (focus/tracking loop offset, balance, loop gain)

- Built-in AGC feature that adapts to work optimally with various disc types

- Built-in search algorithm for speed control

- Servo monitor signal generation (FOK, MIRROR, TZC, ANTI-SHOCK)

- Various loop filter coefficient selection by MICOM

- Built-in algorithm for handling defects/shocks

- Disc discriminating data out (FEpk, SBADpk)

- RF IC and serial interface

- Built-in 10-bit DAC (Focus/Tracking/SLD)

- OAK DSP core

• CD Digital Signal Processing Block

- Wide capture range analog PLL

- Data Slicer using duty feedback method

- EFM demodulation

- Sync detection, protection, insertion

- CLV, CAV disc spindle motor control

- C1/C2 ECC

- Built-in 16 K SRAM for ECC

- Subcode P - W handling feature

- CD-DA Audio handling feature

- SUB-Q De-interleaving & CRC check

- High speed data transmission support by CD-ROM decoder block for audio buffering (sync mode selection between subcode sync and CD-DA data)

- Digital audio out block

- Subcode sync. Insertion, Protection

• 1-Bit DAC

- 16-bit å D digital-to-analog converter

- On-chip analog postfilter

- Filtered line-level outputs, linear phase filtering

- 90dB SNR

- Sampling rate: 44.1kHz

- Input rate 1Fs or 2Fs by normal mode/ double mode selection

- Digital volume control by MICOM interface

- On-chip voltage reference

- Digital de-emphasis on/off, digital attenuation

- Low clock jitter sensitivity

• Technology & Gate Density

- 0.35um mixed mode CMOS technology

- 3.3V power supply (internal core & analog)

- 5.0V power supply (digital I/O)

- Current used: 300mA

- Package: 128QFP.

- Core used: OAK DSP; ADC for servo use; DAC, 1-bit DAC; 16K SRAM.

- Clock used:

1) 33.8688MHz & PLL clock (4.3218MHz * speed coeff.) ® DP part.

2) 33.8688MHz or 40MHz synthesized frequency ® servo part.

3) 16.9344MHz ® 1-bit DAC part.