7 watt; Torpedo Compact Fluorescent; 2700K; 82 CRI; Medium base; 120 volts

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SATCO

DDR TERMINATION REGULATOR

DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to pro

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UTC

友顺

DDR TERMINATION REGULATOR

文件：218.33 Kbytes 页数：12 Pages

ETL

亚历电子

DDR TERMINATION REGULATOR

文件：219.14 Kbytes 页数：12 Pages

UTC

友顺