S3029A中文资料应用微电路公司数据手册PDF规格书

GENERAL DESCRIPTION

The function of the S3029 clock synthesis and recovery unit is to derive high speed timing signals for SONET/SDH-based equipment. The S3029 is implemented using AMCC’s proven Phase Locked Loop (PLL) technology.

FEATURES

• Complies with ANSI, Bellcore, and ITU-T specifications for jitter tolerance, jitter generation

• Five on-chip high frequency PLLs with internal loop filters for clock recovery

• Supports clock recovery for STS-3/STM-1 (155.52 Mbit/s) NRZ data

• Clock Multiplier PLL for transmit clock generation

• 19.44 or 51.84 MHz reference frequency

• Lock detect—monitors run length and frequency

• Low-jitter differential interface

• 3.3V supply

• Available in a 64-pin TQFP package

• Compatible with IgT WAC-413 ATM Quad-UNI processor