S28HS256T中文资料英飞凌数据手册PDF规格书

Features

• Infineon 45 nm MIRRORBIT™ technology that stores two data bits in each memory array cell

• Sector architecture options

- Uniform: Address space consists of all 256 KB sectors

- Hybrid:

• Configuration 1 - Address space consists of thirty-two 4 KB sectors grouped either on the top or the bottom

while the remaining sectors are all 256 KB

• Configuration 2 - Address space consists of thirty-two 4 KB sectors equally split between top and bottom

while the remaining sectors are all 256 KB

• Page programming buffer of 256 or 512 bytes

• OTP secure silicon array of 1024 bytes (32 × 32 bytes)

• Octal interface (8S-8S-8S, 8D-8D-8D)

- JEDEC eXpanded serial peripheral interface (SPI) (JESD251) compliant

- SDR option runs up to 200 MBps (200 MHz clock speed)

- DDR option runs up to 400 MBps (200 MHz clock speed)

- Supports data strobe (DS) to simplify the read data capture in high-speed systems

• SPI (1S-1S-1S, 1S-1S-8S, 1S-8S-8S)

- JEDEC eXpanded SPI (JESD251) compliant

• Functional safety features

- Functional safety ISO26262 ASIL B compliant and ASIL D ready

- Infineon Endurance Flex architecture provides high-endurance and long retention partitions

- Interface CRC detects errors on communication interface between host controller and SEMPER™ Flash device

- Data integrity CRC detects errors in memory array

- SafeBoot reports device initialization failures, detects configuration corruption and provides recovery options

- Built-in error correcting code (ECC) corrects single-bit error and detects double-bit error (SECDED) on memory

array data

- Sector erase status indicator for power loss during erase

• Protection features

- Legacy block protection (LBP) for memory array and device configuration

- Advanced sector protection (ASP) for individual memory array sector based protection

• AutoBoot enables immediate access to the memory array following power-on

• Hardware reset through CS# signaling method (JEDEC) OR individual RESET# pin

• Serial flash discoverable parameters (SFDP) describing device functions and features

• Device identification, manufacturer identification and unique identification

• Data integrity

• Min. 512,000 program-erase cycles for the main array

• Min. 300,000 program-erase cycles for the 4 KB sectors

• Minimum 25 years data retention

• Supply voltage

- 1.7 V to 2.0 V (HS-T)

- 2.7 V to 3.6 V (HL-T)

• Grade / temperature range

- Industrial (–40°C to +85°C)

- Industrial plus (–40°C to +105°C)

- Automotive AEC-Q100 grade 3 (–40°C to +85°C)

- Automotive AEC-Q100 grade 2 (–40°C to +105°C)

- Automotive AEC-Q100 grade 1 (–40°C to +125°C)

• Packages

- 24-ball BGA 6 × 8 mm