QL8X12B-1PL68M中文资料pASIC 1 Family Very-High-Speed CMOS FPGA数据手册QuickLogic规格书

描述 Description

PRODUCT SUMMARY
The QL8x12B is a member of the pASIC 1 Family of very-high-speed CMOS user-programmable ASIC devices. The 96 logic cell field programmable gate array (FPGA) offers 1,000 usable “gate array” gates (equivalent to 2,000 usable PLD gates) of high-performance general purpose logic in 44-pin and 68-pin PLCC packages and 100-pin TQFP packages.FEATURES
Total of 64 I/O pins
  – 56 Bidirectional Input/Output pins
  – 6 Dedicated Input/High-Drive pins
  – 2 Clock/Dedicated input pins with fanout-independent, low-skew clock networks
Input + logic cell + output delays under 6 ns
Chip-to-chip operating frequencies up to 110 MHz
Internal state machine frequencies up to 150 MHz
Clock skew < 0.5 ns
Input hysteresis provides high noise immunity
Built-in scan path permits 100% factory testing of logic and I/O cells and functional testing with Automatic Test Vector Generation (ATVG) software after programming
Available packages are 44- and 68-pin PLCC, and a 100-pin TQFP
68-pin PLCC compatible with QL12x16B
100-pin TQFP compatible with QL12x16B and QL16x24B
0.65µ CMOS process with ViaLink programming technology

特性 Features

Total of 64 I/O pins
  – 56 Bidirectional Input/Output pins
  – 6 Dedicated Input/High-Drive pins
  – 2 Clock/Dedicated input pins with fanout-independent, low-skew clock networks
Input + logic cell + output delays under 6 ns
Chip-to-chip operating frequencies up to 110 MHz
Internal state machine frequencies up to 150 MHz
Clock skew < 0.5 ns
Input hysteresis provides high noise immunity
Built-in scan path permits 100% factory testing of logic and I/O cells and functional testing with Automatic Test Vector Generation (ATVG) software after programming
Available packages are 44- and 68-pin PLCC, and a 100-pin TQFP
68-pin PLCC compatible with QL12x16B
100-pin TQFP compatible with QL12x16B and QL16x24B
0.65µ CMOS process with ViaLink programming technology