首页>QL3012>规格书详情

QL3012中文资料PDF规格书

QL3012
厂商型号

QL3012

功能描述

60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density

文件大小

239.12 Kbytes

页面数量

14

生产厂商 List of Unclassifed Manufacturers
企业简称

ETC1etc未分类制造商

中文名称

未分类制造商官网

原厂标识
数据手册

下载地址一下载地址二原厂数据手册到原厂下载

更新时间

2024-6-19 22:50:00

QL3012规格书详情

[QUICK LOGIC]

Product Summary

The pASIC 3 FPGA family features up to 60,000 usable PLD gates. pASIC 3 FPGAs are fabricated on a 0.35mm four-layer metal process using Quick Logic’s patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use.

Device Highlights

High Performance and High Density

■60,000 Usable PLD Gates with 316 I/Os

■16-bit counter speeds over 300 MHZ, data path speeds over 400 MHz

■0.35um four-layer metal non-volatile CMOS process for smallest die sizes

Easy to Use/Fast Development Cycles

■100 routable with 100 utilization and complete pin-out stability

■Variable-grain logic cells provide high performance and 100 utilization

■Comprehensive design tools include high quality Verilog/VHDL synthesis

Advanced I/O Capabilities

■Interfaces with both 3.3 volt and 5.0 volt devices

■PCI compliant with 3.3V and 5.0V buses for -1/-2 speed grades

■Full JTAG boundary scan

■Registered I/O cells with individually controlled clocks and output enables

Features

Total of 180 I/O pins

■308 bidirectional input/output pins, PCI-compliant for 5.0 volt and 3.3 volt buses for -1/-2 speed grades

■8 high-drive input/distributed network pins Eight Low-Skew Distributed Networks

■Two array clock/control networks available to the logic cell flip-flop clock, set and reset inputs - each

driven by an input-only pin

■Up to six global clock/control networks available to the logic cell F1, clock, set and reset inputs and the input and I/O register clock, reset and enable inputs as well as the output enable control - each driven by an input-only or I/O pin, or any logic cell output or I/O cell feedback High Performance

■Input + logic cell + output total delays under 6 ns

■Data path speeds exceeding 400 MHz

■Counter speeds over 300 MHz

产品属性

  • 型号:

    QL3012

  • 功能描述:

    60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density

供应商 型号 品牌 批号 封装 库存 备注 价格
QUICKLOGIC
23+
QFP
20000
全新原装假一赔十
询价
LSSJ
1736+
PLCC84
8298
只做进口原装正品假一赔十!
询价
QUICKLOGIC
589220
16余年资质 绝对原盒原盘 更多数量
询价
QUICKLOGIC
QFP
68500
一级代理 原装正品假一罚十价格优势长期供货
询价
QUIKLOGIC
22+
PLCC84
6000
进口原装 假一罚十 现货
询价
QUIKLOGIC
9926+
PLCC84
880000
明嘉莱只做原装正品现货
询价
QUICKLOGIC
22+
QFP
2897
只做原装自家现货供应!
询价
QUICKLOGIC
2023+
TQFP
700000
柒号芯城跟原厂的距离只有0.07公分
询价
QUICKLOG
2018+
BGA
25000
进口原装现货
询价
QUALCOMM
2138+
TQFP
8960
专营BGA,QFP原装现货,假一赔十
询价