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QL2003-1PF100I中文资料PDF规格书
QL2003-1PF100I规格书详情
[QuickLogic]
PRODUCT SUMMARY
The QL2003 is a 3,000 usable ASIC gate, 5,000 usable PLD gate member of the pASIC 2 family of FPGAs. pASIC 2 FPGAs employ a unique combination of architecture, technology, and software tools to provide high speed, high usable density, low price, and flexibility in the same devices. The flexibility and speed make pASIC 2 devices an efficient and high performance silicon solution for designs described using HDLs such as Verilog and VHDL, as well as schematics.
FEATURES
Ultimate Verilog/VHDL Silicon Solution
- Abundant, high-speed interconnect eliminates manual routing
- Flexible logic cell provides high efficiency and performance
- Design tools produce fast, efficient Verilog/VHDL synthesis
Speed, Density, Low Cost and Flexibility in One Device
- 16-bit counter speeds exceeding 200 MHz
- 3,000 usable ASIC gates, 5,000 usable PLD gates, 118 I/Os
- 3-layer metal ViaLink process for small die sizes
- 100 routable and pin-out maintainable
Advanced Logic Cell and I/O Capabilities
- Complex functions (up to 16 inputs) in a single logic cell
- High synthesis gate utilization from logic cell fragments
- Full IEEE Standard JTAG boundary scan capability
- Individually-controlled input/feedback registers and OEs on all I/O pins
Other Important Family Features
- 3.3V and 5.0V operation with low standby power
- I/O pin-compatibility between different devices in the same packages
- PCI compliant (at 5.0V), full speed 33 MHz implementations
- High design security provided by security fuses
Total of 118 I/O Pins
- 110 bidirectional input/output pins, PCI-compliant at 5.0V in -1/-2 speed grades
- 4 high-drive input-only pins
- 4 high-drive input/distributed network pins
Four Low-Skew (less than 0.5ns) Distributed Networks
- Two array networks available to logic cell flip-flop clock, set, and reset - each driven by an input-only pin
- Two global clock/control networks available to F1 logic input, and logic cell flip-flop clock, set, reset; input and I/O register clock, reset, enable; and output enable controls - each driven by an input-only pin, or any input or I/O pin, or any logic cell output or I/O cell feedback
High Performance
- Input + logic cell + output delays under 6 ns
- Datapath speeds exceeding 225 MHz
- Counter speeds over 200 MHz
产品属性
- 型号:
QL2003-1PF100I
- 功能描述:
Field Programmable Gate Array(FPGA)
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
QUICKLOGIC |
22+ |
QFP |
3000 |
原装现货 |
询价 | ||
QUALCOMM |
16+ |
QFP |
2500 |
进口原装现货/价格优势! |
询价 | ||
QUICKL |
22+ |
QFP |
5623 |
只做原装正品现货!或订货假一赔十! |
询价 | ||
QUICKLOG |
21+ |
QFP |
13880 |
公司只售原装,支持实单 |
询价 | ||
QUICKLOG |
23+ |
QFP |
10880 |
原装正品,支持实单 |
询价 | ||
QUICKL |
02+ |
QFP |
4 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
询价 | ||
QUICKL |
589220 |
16余年资质 绝对原盒原盘 更多数量 |
询价 | ||||
QUICKLOGIC |
1116+ |
PLCC84 |
6869 |
绝对原装现货 |
询价 | ||
QUICKL |
QFP |
899933 |
集团化配单-有更多数量-免费送样-原包装正品现货-正规 |
询价 | |||
QUKLOG |
23+ |
NA/ |
105 |
优势代理渠道,原装正品,可全系列订货开增值税票 |
询价 |