QL12X16B-PQ208M中文资料ETC数据手册PDF规格书

[QuickLogic]

PRODUCT SUMMARY

The pASIC 1 Family is a very-high-speed CMOS user-programmable ASIC devices. The 768 logic cell field-programmable gate array (FPGA) features 22,000 usable PLD gates of high-performance general-purpose logic in a 208-pin PQFP and CQFP package.

DEVICE HIGHLIGHTS

Very High Speed

■ ViaLink“ metal-to-metal programmable technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns at 5V, and over 80 MHz at 3.3V operation.

High Usable Density

■ Up to a 24-by-32 array of 768 logic cells provides 22,000 usable PLD gates in 208-pin PQFP and 208-pin CQFP packages.

PCI-Output Drive

■ Fully PCI 2.1 compliant input/output capability. (including drive current)

FEATURES

■ Total of 180 I/O pins

■ -172 Bidirectional Input/Output pins

■ -6 Dedicated Input/High-Drive pins

■ -2 Clock/Dedicated input pins with fanoutindependent, low-skew clock networks

■ -PCI 2.1 Compliant I/Os

■ Input + logic cell + output delays under 6 ns

■ Chip-to-chip operating frequencies up to 110 MHz

■ Internal state machine frequencies up to 150 MHz

■ Clock skew < 0.5 ns

■ Input hysteresis provides high noise immunity

■ Built-in scan path permits 100 factory testing of logic and I/O cells and functional testing with Automatic Test Vector Generation (ATVG) software after programming

■ 208 pin PQFP pin for pin compatible with the 208 CQFP

■ 0.65µ CMOS process with ViaLink programming technology