PX1011B-EL1数据手册恩XP中文资料规格书

描述 Description

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The PX1011B is a high-performance, low-power, single-lane PCI Express electrical PHYsical layer (PHY) that handles the low-level PCI Express protocol and signaling. The PX1011B PCI Express PHY is compliant to the PCI Express Base Specification, Rev. 1.0a, and Rev. 1.1. The PX1011B includes features such as Clock and Data Recovery (CDR), data serialization and de-serialization, 8b/10b encoding, analog buffers, elastic buffer and receiver detection, and provides superior performance to the Media Access Control (MAC) layer devices.
The PX1011B is a 2.5 Gbit/s PCI Express PHY with 8-bit data PXPIPE interface. Its PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE) specification, enhanced and adapted for off-chip applications with the introduction of a source synchronous clock for transmit and receive data. The 8-bit data interface operates at 250 MHz with SSTL_2 signaling. The SSTL_2 signaling is compatible with the I/O interfaces available in FPGA products.
The PX1011B PCI Express PHY supports advanced power management functions. The PX1011BI is for the industrial temperature range (-40 ℃ to +85 ℃). Automotive AEC-Q100 compliant version PX1011B-EL1/Q900 is available.

特性 Features

2.1 PCI Express interface
• Compliant to PCI Express Base Specification 1.1
• Single PCI Express 2.5 Gbit/s lane
• Data and clock recovery from serial stream
• Serializer and De-serializer (SerDes)
• Receiver detection
• 8b/10b coding and decoding, elastic buffer and word alignment
• Supports loopback
• Supports direct disparity control for use in transmitting compliance pattern
• Supports lane polarity inversion
• Low jitter and Bit Error Rate (BER)