PTN3381DBS数据手册恩XP中文资料规格书

描述 Description

The PTN3381D is a high-speed level shifter device which converts four lanes of low-swingAC-coupled differential input signals to DVI v1.0 and HDMI v1.4b compliant open-draincurrent-steering differential output signals, up to 3 Gbit/s to support 36-bit deep color, 3Dand 3 Gbit/s modes. Each of these channels provides a level-shifting differential buffer totranslate from low-swing AC-coupled differential signaling on the source side, toTMDS-type DC-coupled differential current-mode signaling terminated into 50 Ω to 3.3 Von the sink side. Additionally, the PTN3381D provides a single-ended active buffer forvoltage translation of the HPD signal from 5 V on the sink side to 3.3 V on the source sideand provides a channel with active buffering and level shifting of the DDC channel(consisting of a clock and a data line) between 3.3 V source-side and 5 V sink-side. TheDDC channel is implemented using active I²C-bus buffer technology providing capacitiveisolation, redriving and level shifting as well as disablement (isolation between source andsink) of the clock and data lines.
To provide the highest level of integration in external adapter (or: dongle) applications,PTN3381D includes an on-board 5 V DC regulator. Its output is designed to provide therequired 5 V power supply to the DVI or HDMI connector, thereby eliminating the need fora separate external regulator. The on-board regulator needs only two external capacitorsto operate, and its output is active whenever a valid 3.3 V is applied to the PTN3381D VDDpins.
The low-swing AC-coupled differential input signals to the PTN3381D typically come froma display source with multi-mode I/O, which supports multiple display standards, forexample, DisplayPort, HDMI and DVI. While the input differential signals are configured tocarry DVI or HDMI coded data, they do not comply with the electrical requirements of theDVI v1.0 or HDMI v1.3a specification. By using PTN3381D, chip set vendors are able toimplement such reconfigurable I/Os on multi-mode display source devices, allowing thesupport of multiple display standards while keeping the number of chip set I/O pins low.
The PTN3381D main high-speed differential lanes feature low-swing self-biasingdifferential inputs which are compliant to the electrical specifications of DisplayPortStandard v1.2 and/or PCI Express Standard v1.1, and open-drain current-steeringdifferential outputs compliant to DVI v1.0 and HDMI v1.4b electrical specifications.TheI²C-bus channel actively buffers as well as level-translates the DDC signals for optimalcapacitive isolation. Its I²C-bus control block also provides for optional software HDMIdongle detect by issuing a predetermined code sequence upon a read command to anI²C-bus specified address. The PTN3381D also supports power-saving modes in order tominimize current consumption when no display is active or connected.
The PTN3381D is a fully featured HDMI as well as DVI level shifter. It is functionallyequivalent to PTN3361D but provides an onboard 5 V regulator. The PTN3381Dsupersedes PTN3381B, and provides a better high speed performance with aprogrammable equalizer.
PTN3381D is powered from a single 3.3 V power supply consuming a small amount ofpower (230 mW typical with no load at 5 V regulator) and is offered in a 48-terminalHVQFN48 package.

特性 Features

High-speed TMDS level shifting
• Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 andHDMI v1.4b compliant open-drain current-steering differential output signals
• TMDS level shifting operation up to 3 Gbit/s per lane (300 MHz character clock)supporting 36-bit deep color, 3D and 3 Gbit/s modes
• Programmable equalizer
• Integrated 50 Ω termination resistors for self-biasing differential inputs
• Back-current safe outputs to disallow current when device power is off and monitor ison
• Disable feature to turn off TMDS inputs and outputs and to enter low-power state
DDC level shifting
• Integrated DDC buffering and level shifting (3.3 V source to 5 V sink side)
• Rise time accelerator on sink-side DDC ports
• 100 kHz I²C-bus clock frequency
• Back-power safe sink-side terminals to disallow backdrive current when power is off orwhen DDC is not enabled
HDMI dongle detect support
• Incorporates I²C slave ROM
• Responds to DDC read to address 81h with predetermined byte sequence
• Feature enabled by pin DDET (must be enabled for correct operation in accordancewith DisplayPort interoperability guideline)
HPD level shifting
• HPD non-inverting level shift from 0 V on the sink side to 0 V on the source side, orfrom 5 V on the sink side to 3.3 V on the source side
• Integrated 200 kΩ pull-down resistor on HPD sink input guarantees ‘input LOW’ whenno display is plugged in
• Back-power safe design on HPD_SINK to disallow backdrive current when power is off
5 V DC voltage regulator
• Generates 5 V for the DVI/HDMI connector from the 3.3 V DP_PWR pin supplied bythe DisplayPort connector
• Supports up to 75 mA of load current with an accuracy of ±300 mV
• Only two external capacitors required
• Eliminates need for an external 5 V regulator in dongle applications
• Back drive protection on 5 V output
• Short-circuit protection
• Overcurrent protection
General
• Power supply 2.85 V to 3.6 V
• ESD resilience to 6 kV HBM, 1 kV CDM
• Power-saving modes (using output enable)
• Back-current-safe design on all sink-side main link, DDC and HPD terminals
• Transparent operation: no re-timing or software configuration required

应用 Application

支持36位深色域、3D和3 Gbit/s模式的DisplayPort至HDMI适配器
需要驱动长电缆的DisplayPort至DVI适配器