PMB2306中文资料西门子数据手册PDF规格书

General Description

The circuit consists of a reference-, a- and n-counter, a dual modulus control logic, a phase detector with charge pump output and a serial control logic. The setting of the operating mode and the selection of the counter ratios is done serially at the ports CLK, DA and EN.

The operating modes allow the selection of single or dual operation, asynchronous or synchronous data acquisition, 4 different antibacklash-impulse times, 8 different PDoutput current modes, polarity setting of the PD-output signal, adjustment of the triggeredge of the MOD-output signal, 2 standby modes and the control of the multifunction outputs MFO1 and MFO2.

The reference frequency is applied at the RI-input and scaled down by the r-counter. It’s maximum value is 100 MHz. The VCO-frequency is applied at the FI-input and scaled down by the n- or n/a-counter according to single or dual mode operation. The maximum value at FI is 220 MHz at single-, and 65 MHz at dual mode operation.

Features

• Low operating current consumption (typically 3.5 mA)

• High input sensitivity, high input frequencies (220 MHz)

• Extremely fast phase detector without dead zone

• Linearization of the phase detector output by current sources

• Synchronous programming of the counters (n-, n/a-, r-counters) and system parameters

• Fast modulus switchover for 65-MHz operation

• Switchable modulus trigger edge

• Large dividing ratios for small channel spacing

A scaler 0 to 127

N scaler 3 to 16.380

R scaler 3 to 65.535

• Serial control (3-wire bus: data, clock, enable) for fast programming (Imax ~ 10 MHz)

• Switchable polarity and phase detector current programmable

• 2 Multifunction outputs

• Digital phase detector output signals (e.g. for external charge pump)

• Irn, Ivn outputs of the R and N scalers

• Port 1 output (e.g. for standby of the prescaler)

• External current setting for PD output

• Lock detect output with gated anti-backlash pulse (quasi digital lock detect)