PM7520C数据手册MaxLinear中文资料规格书

描述 Description

The SyntheCLK is a clock synthesizer with an integrated jitter attenuator. It provides multi-output clock generation and distribution using a cascaded phase- locked loop(PLL) architecture with programmable dividers and clock drivers.

 

The Jitter Attenuator (JAT) PLL filters jitter on the incoming reference clock and synchronizes the external voltage controlled crystal oscillator (VCXO).

 

By cascading the clock synthesizer PLL with the JAT PLL, this architecture provides clean output clocks using a low cost, low frequency VCXO which is ideal for wireless base-station applications requiring highly integrated low power clocking solutions.

特性 Features

·Generates low jitter, low phase noise clock outputs for driving high performance data converters, RF synthesizers, SERDES, and DSP subsystems
·Output frequency is SPI programmable for up to 30 clock outputs

应用 Application

·Low jitter, low phase noise clock distribution
·Clocking high performance ADCs, DACs, RF Synthesizers, FPGAs
·High performance wireless transceivers
·Broadband wireless infrastructure