PM7324-1中文资料PMC数据手册PDF规格书

FEATURES

• Monolithic single chip device which handles bi-directional ATM Layer functions including VPI/VCI address translation, cell appending, policing (ingress only), cell counting and OAM requirements for 65536 VCs (virtual connections).

• Instantaneous bi-directional transfer rate of 800 Mbit/s supports a bidirectional cell transfer rate of 1.42x106 cells/s.

• Ingress input interface supports an 8 or 16 bit PHY interface using direct addressing for up to 4 PHY devices (Utopia Level 1) and Multi-PHY addressing for up to 32 PHY devices (Utopia Level 2).

• Ingress output interface supports an 8 or 16 bit SCI-PHY (52 - 64 byte cell) interface (Utopia Level 1) to a switch fabric.

• Egress input and output interfaces support an 8 or 16 bit SCI-PHY (52 - 64 byte cell) interface using direct addressing for up to 4 PHY devices (Utopia Level 1) and Multi-PHY addressing for up to 32 PHY devices (Utopia Level 2).

• Compatible with a wide range of switching fabrics and traffic management architectures.

• Ingress functionality includes a highly flexible search engine that covers the entire PHYID/VPI/VCI address range, dual leaky bucket policing, per-VC cell counts, OAM-FM and OAM-PM processing.

• Egress functionality includes direct address lookup, per-VC cell counts, OAM-FM and OAM-PM processing. Per-PHY output buffering scheme resolves the head-of-line blocking issue.

• Includes a FIFO buffered 16-bit microprocessor bus interface for cell insertion and extraction, deterministic VC Table access, status monitoring and configuration of the device.

• Supports DMA access for cell extraction.

• The UTOPIA and external SRAM interfaces are 52 MHz max.

APPLICATIONS

• WAN ATM Core and Edge Switches

• ATM Enterprise and Workgroup Switches

• Access Switches/Multiplexers