PM73121-RI中文资料AAL1 Segmentation And Reassembly Processor数据手册PMC-Sierra规格书

描述 Description

The AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator II™) provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage of the configuration, the user data, and the statistics. The device provides a microprocessor interface for configuration, management, and statistics gathering. PMC-Sierra also offers a software device control package for the AAL1gator II device.FEATURES
Circuit Interface

特性 Features

Circuit Interface Features
• Provides AAL1 segmentation and reassembly of eight 2 Mbit/s data streams or one 45 Mbit/s or less data stream.
• Supports 256 Virtual Channels (VCs) (32 per line).
• Supports n × 64 structured data format.
• Supports arbitrary timeslot-to-VC mappings, including alternating timeslots.
• Provides Common Channel Signaling (CCS) and Channel Associated Signaling (CAS) configuration options.
• Provides per-VC data and signaling conditioning in both the transmit and the receive directions.
• Arbitrates a 16-bit microprocessor interface to a 128K × 16 (12 ns) SRAM.
• Supports multicast connections, ATM Monitoring (AMON), Remote Monitoring (RMON), and ATM Circuit Steering (ACS).
• Supports adaptive clocking in Structured Data Format, Frame-based (SDF-FR), Structured Data Format, Multiframe-based (SDF-MF), and Unstructured Data Format, Multiple Line (UDF-ML) modes.Transmit Cell Interface Features
• Provides an ATM-layer or PHY-layer 33 MHz UTOPIA interface. Both Single PHY (SPHY) and Multi-PHY (MPHY) modes are supported.
• Provides per-VC transmit queueing.
• Provides a calendar queue service algorithm that produces minimal Cell Delay Variation (CDV).
• Provides a supervisory transmit buffer for Operations, Administration, and Maintenance (OAM), and for ATM signaling.
• Generates pointers for structured data transmission.
• Provides sequence number and sequence number protection generation.
• Provides partially filled cell generation with the length configurable on a per-VC basis.
• Generates and transmits Synchronous Residual Time Stamp (SRTS) values for unstructured modes.
• Built-in transmit line clock generation based on received SRTS values, receive line clock, or a nominal frequency.Receive Cell Interface Features
• Provides an ATM-layer or PHY-layer 33 MHz UTOPIA interface. Both SPHY and MPHY modes are supported.
• Provides per-VC queues.
• Provides per-VC CDV tolerance settings.
• Provides per-VC partially filled cell length settings.
• Provides a supervisory receive queue for OAM cells.
• Verifies and corrects sequence numbers in accordance with ITU-T Recommendation I.363.1.
• Processes sequence numbers in accordance with the “Fast SN Algorithm”, as specified in the ITU-T Recommendation I.363.1.
• Maintains bit integrity through individual errored cells or up to six lost cells. Takes into account pointer bytes.
• During underruns, can output fixed, pseudorandom, or old data.
• Provides processor interrupts for OAM cell receptions.
• Provides a multiplexed interface to external receive Phase-Locked Loops (PLLs) for SRTS clock recovery for unstructured modes or adaptive clock recovery.Statistics Features
• Counts invalid Cyclic Redundancy Check (CRC) values for sequence numbers.
• Counts OAM cells and dropped OAM cells.
• Counts data cells transmitted per VC.
• Counts conditioned data cells transmitted per VC.
• Counts cells not transmitted due to line resynchronization per VC.
• Counts cells received, dropped, lost, or misinserted per VC.
• Counts cells with incorrect Sequence Number (SN) or incorrect Sequence Number Protection (SNP).
• Counts underrun occurrences per VC.
• Counts overrun occurrences per VC.
• Counts pointer reframes and pointer parity errors per VC.