PM4341A中文资料PMC数据手册PDF规格书

FEATURES

• Integrates a full-featured T1 framer and line interface in a single device with

analog circuitry for receiving and transmitting DSX-1 compatible signals and

digital circuitry for terminating the duplex DS-1 signal.

• Provides an 8-bit microprocessor bus interface for configuration, control, and

status monitoring.

• Low power CMOS technology

• Available in either a 68 pin PLCC package, or a high density (14 by 14mm) 80

pin PQFP package.

The receiver section:

• Provides analog circuitry for receiving a DSX-1 signal up to 655 feet from the

cross-connect. Direct digital inputs are also provided to allow for by-passing

the analog front-end.

• Recovers clock and data using a digital phase locked loop for high jitter

tolerance. A direct clock input is provided to allow clock recovery to be bypassed.

• Accepts dual rail or single rail digital PCM inputs.

• Supports B8ZS or AMI line code.

• Accepts gapped data streams to support higher rate demultiplexing.

• Frames to SF, ESF, T1DM (DDS), and SLC®96 format DS1 signals.

• Provides loss of signal detection, and red, yellow, and AIS alarm detection.

Red, yellow, and AIS alarms are integrated as per industry specifications.

• Detects violations of the ANSI T1.403 12.5 pulse density rule over a moving

192 bit window.

• Provides programmable in-band loopback code detection.

• Supports line and path performance monitoring according to AT&T and ANSI

specifications. Accumulators are provided for counting:

• ESF CRC-6 errors to 333 per second;

• Framing bit errors to 31 per second;

• Line code violations to 4095 per second; and

• Loss of frame or change of frame alignment events to 7 per

second.

• Provides ESF bit-oriented code detection, and an HDLC/LAPD interface for

terminating the ESF data link.

• Supports polled, interrupt-driven, or DMA servicing of the HDLC interface.

• Extracts the data link in ESF, T1DM (DDS) or SLC®96 modes. Extracts the Dchannel for Primary Rate interfaces.

• Provides a two-frame elastic store buffer for jitter and wander attenuation that

performs controlled slips and indicates slip occurrence and direction.

• Provides robbed bit signalling extraction, with optional data inversion,

programmable idle code substitution, digital milliwatt code substitution, bit

fixing, and 2 superframes of signalling debounce on a per-channel basis.

• Provides trunk conditioning which forces programmable trouble code

substitution and signalling conditioning on all channels or on selected

channels.

• Optionally provides dual rail digital PCM output signals to allow BPV

transparency. Also supports unframed mode.

• Supports transfer of received PCM and signalling data to 1.544 Mbit/s

backplane buses or to 2.048 Mbit/s backplane buses.

APPLICATIONS

• T1 Channel Service Units (CSU) and Data Service Units (DSU)

• T1 Channel Banks (CH BANK) and Multiplexers (CPE MUX)

• Digital Private Branch Exchanges (DPBX)

• Digital Access and Cross-Connect Systems (DACS) and Electronic DSX Cross-Connect Systems (EDSX)

• T1 Frame Relay Interfaces

• T1 ATM Interfaces

• ISDN Primary Rate Interfaces (PRI)

• SONET Add/Drop Multiplexers (ADM)

• Test Equipment