PLUS405-37A中文资料Programmable logic sequencers (16 × 64 × 8)数据手册恩XP规格书

描述 Description

DESCRIPTION
The PLUS405 devices are bipolar, programmable state machines of the Mealy type. Both the AND and the OR array are user-programmable. All 64 AND gates are connected to the 16 external dedicated inputs (I0 - I15) and to the feedback paths of the 8 on-chip State Registers (QP0 - QP7). Two complement arrays support complex IF-THEN-ELSE state transitions with a single product term (input variables C0, C1).
All state transition terms can include True, False and Don’t Care states of the controlling state variables. All AND gates are merged into the programmable OR array to issue the next-state and next-output commands to their respective registers. Because the OR array is programmable, any one or all of the 64 transition terms can be connected to any or all of the State and Output Registers.FEATURES
• PLUS405-37
   – fMAX = 37MHz
   – 50MHz clock rate
• PLUS405-45
   – fMAX = 45MHz
   – 58.8MHz clock rate
• Functional superset of PLS105/105A
• Field-programmable (Ti-W fusible link)
• 16 input variables
• 8 output functions
• 64 transition terms
• 8-bit State Register
• 8-bit Output Register
• 2 transition Complement Arrays
• Multiple clocks*
• Programmable Asynchronous Initialization or Output Enable
• Power-on preset of all registers to “1”
• “On-chip” diagnostic test mode features for access to state and output registers
• 950mW power dissipation (typ.)
• TTL compatible
• J-K or S-R flip-flop functions
• Automatic “Hold” states
• 3-State outputsAPPLICATIONS
• Interface protocols
• Sequence detectors
• Peripheral controllers
• Timing generators
• Sequential circuits
• Elevator contollers
• Security locking systems
• Counters
• Shift registers

特性 Features

• PLUS405-37
   – fMAX = 37MHz
   – 50MHz clock rate
• PLUS405-45
   – fMAX = 45MHz
   – 58.8MHz clock rate
• Functional superset of PLS105/105A
• Field-programmable (Ti-W fusible link)
• 16 input variables
• 8 output functions
• 64 transition terms
• 8-bit State Register
• 8-bit Output Register
• 2 transition Complement Arrays
• Multiple clocks*
• Programmable Asynchronous Initialization or Output Enable
• Power-on preset of all registers to “1”
• “On-chip” diagnostic test mode features for access to state and output registers
• 950mW power dissipation (typ.)
• TTL compatible
• J-K or S-R flip-flop functions
• Automatic “Hold” states
• 3-State outputs