PLL1705数据手册集成电路（IC）的时钟发生器PLL频率合成器规格书PDF

描述 Description

The PLL1705 are low cost, phase-locked loop (PLL) multiclock generators. The PLL1705 and PLL1706 can generate four system clocks from a 27-MHz reference input frequency. The clock outputs of the PLL1705 can be controlled by sampling frequency-control pins and those of the PLL1706 can be controlled through serial-mode control pins. The device gives customers both cost and space savings by eliminating external components and enables customers to achieve the very low-jitter performance needed for high performance audio DACs and/or ADCs. The PLL1705 and PLL1706 are ideal for MPEG-2 applications which use a 27-MHz master clock such as DVD players, DVD add-on cards for multimedia PCs, digital HDTV systems, and set-top boxes.

特性 Features

• 27-MHz Master Clock Input
• Generated Audio System Clock:
- SCKO0: 768 fS (fS = 44.1 kHz)
• SCKO1: 384 fS, 768 fS (fS = 44.1 kHz)
• SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz)
• SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz)
• Zero PPM Error Output Clocks
• Low Clock Jitter: 50 ps (Typical)
• Multiple Sampling Frequencies:
- fS = 32, 44.1, 48, 64, 88.2, 96 kHz
• 3.3-V Single Power Supply
• PLL1705: Parallel Control PLL1706: Serial Control
• Package: 20-Pin SSOP (150 mil), Lead-Free Product
• APPLICATIONS
- DVD Players
• DVD Add-On Cards for Multimedia PCs
• Digital HDTV Systems
• Set-Top Boxes
The PLL1705 and PLL1706 use the same die and they are electrically identical except for mode control.