PLL1705集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

PLL1705属于集成电路（IC）的时钟发生器PLL频率合成器。由德州仪器制造生产的PLL1705时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。

FEATURES

27-MHz Master Clock Input

Generated Audio System Clock:

− SCKO0: 768 fS (fS = 44.1 kHz)

− SCKO1: 384 fS, 768 fS (fS = 44.1 kHz)

− SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2,

96 kHz)

− SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2,

96 kHz)

Zero PPM Error Output Clocks

Low Clock Jitter: 50 ps (Typical)

Multiple Sampling Frequencies:

− fS = 32, 44.1, 48, 64, 88.2, 96 kHz

3.3-V Single Power Supply

PLL1705: Parallel Control

PLL1706: Serial Control

Package: 20-Pin SSOP (150 mil), Lead-Free

Product

APPLICATIONS

DVD Players

DVD Add-On Cards for Multimedia PCs

Digital HDTV Systems

Set-Top Boxes

DESCRIPTION

The PLL1705† and PLL1706† are low cost, phase-locked

loop (PLL) multiclock generators. The PLL1705 and

PLL1706 can generate four system clocks from a 27-MHz

reference input frequency. The clock outputs of the

PLL1705 can be controlled by sampling frequency-control

pins and those of the PLL1706 can be controlled through

serial-mode control pins. The device gives customers both

cost and space savings by eliminating external

components and enables customers to achieve the very

low-jitter performance needed for high performance audio

DACs and/or ADCs. The PLL1705 and PLL1706 are ideal

for MPEG-2 applications which use a 27-MHz master

clock such as DVD players, DVD add-on cards for

multimedia PCs, digital HDTV systems, and set-top

boxes.