PLL130-68QC-R中文资料PLL数据手册PDF规格书

DESCRIPTION

The PLL130-68 and PLL130-69 are low cost, high performance, high speed, translator buffers that reproduce any input frequency from DC to 1.0GHz. They provide a pair of differential out puts (PECL for PLL130-68 or LVDS for PLL130-69). Thanks to an internal AC coupling of the reference input (REFIN), any input signal with at least 100mV swing can be used as reference signal, regardless of its DC value. These chips are ideal for conversion from clipped sine wave, TTL, CMOS, or differential signal to LVDS or

PECL.

FEATURES

• Differential PECL (PLL130-68) or LVDS(PLL130-69) output.

• Accepts any single-ended REFIN input (with as low as 100mV swing).

• Internal AC coupling of REFIN

• Input range from 1.0MHz to 1.0 GHz.

• No Vref required.

• No external current source required.

• 2.5 to 3.3V operation.

• Available in 3x3mm QFN.