PLL102-03SCL-R规格书库存现货美国申泰PLL-114ic电子网

型号	下载订购	功能描述	制造商上传企业	LOGO
PLL102-03SCL-R	文件：206.13 Kbytes Page：6 Pages	Low Skew Output Buffer DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu 文件：206.13 Kbytes 页数：6 Pages	PLL	PLL
PLL102-03SC-R	文件：206.13 Kbytes Page：6 Pages	Low Skew Output Buffer DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu 文件：206.13 Kbytes 页数：6 Pages	PLL	PLL
TMM-102-03-G-S	文件：1.32206 Mbytes Page：1 Pages	LOW PROFILE THROUGH-HOLE HEADER 文件：1.32206 Mbytes 页数：1 Pages	Samtec 美国申泰	Samtec
TSM-102-03-F-DH	文件：1.51922 Mbytes Page：2 Pages	SMT .025 SQ POST HEADER 文件：1.51922 Mbytes 页数：2 Pages	Samtec 美国申泰	Samtec

更多PLL102-03SCL-R供应商更新时间2025-10-4 15:35:00