PLA133-67数据手册集成电路（IC）的时钟发生器PLL频率合成器规格书PDF

描述 Description

The PLA133-67 is an advanced fanout buffer designed for automotive and other high performance, low-power, small form factor applications. The PLA133-67 accepts a reference clock input from DC to 150 MHz and provides six outputs of the same frequency with ultra-low additive jitter. The device is AEC-Q100 qualified. The PLA133-67 is available in a TSSOP-16L package.

The PLA133-67 outputs can be disabled to a high impedance (tri-state) by pulling low the OE pin. When the OE pin is high, the outputs are enabled and follow the REF input signal. When the OE pin is left open, a pull-up resistor on the chip will default the OE pin to logic 1 so the outputs are enabled.

4-output PLA133-47 https://www.microchip.com/wwwproducts/en/PLA133-47 and 9 output PLA133-97 https://www.microchip.com/wwwproducts/en/PLA133-97 are also available.

特性 Features

• Automotive AEC-Q100 Qualified
• 1:6 LVCMOS Output Fanout Buffer from DC to150 MHz
• Low Additive Phase Jitter of 60 fs RMS
• 8 mA Output Drive Strength
• Automotive Applications Grade 1 Compliant
• Low Input-Output Delay
• Output-Output Skew <250 ps
• 2.5V to 3.3V, ±10% Operation
• 1.8V ±10% Operation up to 67 MHz
• Wide Temperature Range: –40°C to +125°C
• Available in 16-Pin TSSOP Package
Automotive Applications:
• ADAS Vision System
• Infotainment and Dashboard

简介

PLA133-67属于集成电路（IC）的时钟发生器PLL频率合成器。由制造生产的PLA133-67时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。