PL520-30中文资料PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)数据手册Microchip规格书

描述 Description

The PL520-30 is a VCXO IC specifically designed to pull frequency fundamental crystals from 65MHz to 130MHz, with selectable PECL or LVDS outputs and OE logic (enable high or enable low). Its design was optimized to tolerate higher limits of interelectrodes capacitance and bonding capacitance to improve yield.It achieves very low current into the crystal resulting in better overall stability. Its internal varicaps allow an on chip frequency pulling, controlled by the VCON input.

特性 Features

• 65MHz to 130MHz Fundamental Mode Crystals
• Output range (no PLL):
• 65MHz – 130MHz (3.3V)
• 65MHz – 105MHz (2.5V)
• Low Injection Power for crystal 50uW
• Complementary outputs: CMOS, PECL or LVDS
• Selectable OE Logic
• Integrated variable capacitors
• Supports 2.5V or 3.3V Power Supply
• Available in Die form
• Thickness 10mm

简介

PL520-30属于集成电路（IC）的时钟发生器PLL频率合成器。由制造生产的PL520-30时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。