PL500-16中文资料Low Phase Noise LVCMOS VCXO数据手册Microchip规格书

描述 Description

The PL500-15/16 is a low cost, high performance and low phase noise VCXO for the 1MHz to 18MHz range, providing less than -130dBc at 10kHz offset when using a 35.328MHz crystal.The very low jitter (2.5 ps RMS period jitter) makes this chip ideal for applications requiring voltage controlled frequency sources. Input crystal can range from 16MHz to 36MHz (fundamental resonant mode).

特性 Features

• VCXO with Divider Selection (DIVSEL) input pin
• PL500-15: ÷8, ÷16
• PL500-16: ÷2, ÷4
• VCXO output for the 1MHz to 18MHz range
• 16MHz to 36MHz fundamental crystal input
• Low phase noise (-130 dBc @ 10kHz offset using a 35.328MHz crystal)
• LVCMOS output with OE tri-state control
• Integrated high linearity variable capacitors
• 12mA drive capability at TTL output
• ±150 ppm pull range, max 5% linearity
• Low jitter (RMS): 2.5ps period jitter
• 2.5V - 3.3V operation
• Available in 8-Pin SOP, 6-pin SOT23 GREEN/ RoHS compliant packages, or Die

简介

PL500-16属于集成电路（IC）的时钟发生器PLL频率合成器。由制造生产的PL500-16时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。