PL102-10中文资料Buffers数据手册Microchip规格书

描述 Description

The PL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOP or 6-pin SOT23 package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than ±350ps, the device acts as a zero delay buffer.

特性 Features

• Frequency Range:
• 15 to 145MHz @ 2.5V
• Zero Input to Output Delay
• Less Than 200ps Skew Between Outputs
• 2.5V or 3.3V Power Supply
• Available in 8-Pin SOP or 6-pin SOT GREEN/ RoHS Compliant Packages

简介

PL102-10属于集成电路（IC）的时钟发生器PLL频率合成器。由制造生产的PL102-10时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。