Logic level TOPFET

DESCRIPTION Monolithic temperature and overload protected logic level power MOSFET in TOPFET2 technology assembled in a 3 pin surface mount plastic package. FEATURES ● TrenchMOS output stage ● Current limiting ● Overload protection ● Overtemperature protection ● Protection latched reset by

文件：30.17 Kbytes 页数：6 Pages

PHI

PHI

Logic level TOPFET

DESCRIPTION\nMonolithic temperature and overload protected logic level power MOSFET in TOPFET2 technology assembled in a 3 pin surface mount plastic package.FEATURES\n● TrenchMOS output stage\n● Current limiting\n● Overload protection\n● Overtemperature protection\n● Protection latched reset by inpu ● TrenchMOS output stage\n● Current limiting\n● Overload protection\n● Overtemperature protection\n● Protection latched reset by input\n● 5 V logic compatible input level\n● Control of output stage and supply of overload protection\n   circuits derived from input\n● Low operating input current permi;

恩XP

Silicon NPN triple diffusion planar type

文件：89.2 Kbytes 页数：3 Pages

PANASONIC

松下

Silicon NPN Triple-Diffused Planar Type

文件：73.58 Kbytes 页数：1 Pages

PANASONIC

松下

Silicon NPN triple diffusion planar type

文件：89.2 Kbytes 页数：3 Pages

PANASONIC

松下