PI6CB18401数据手册集成电路（IC）的时钟缓冲器驱动器规格书PDF

描述 Description

The PI6CB18401 is an 4-output very low power PCIe Gen1/ Gen2/Gen3 clock buffer. It takes an reference input to fanoutfour 100MHz low power differential HCSL outputs with on-chip terminations. The on-chip termination can save 16 externalresistors and make layout easier. Individual OE pin for each output provides easier power management.It uses Diodes proprietary PLL design to achieve very low jitter that meets PCIe Gen1/Gen2/Gen3 requirements. Other thanPCIe 100MHz support, this device also support Ethernet application with 50MHz or 125MHz via SMBus. It provides variousoptions such as different slew rate and amplitude through strapping pins or SMBUS so that users can configure the device easilyto get the optimized performance for their individual boards.

特性 Features

1.8V supply voltage
HCSL input: 100MHz, also suppport 50MHz or 125MHz via SMBus
4 differential low power HCSL outputs with on-chip termination
Individual output enable
Programmable Slew rate and output amplitute for each output
Differential outputs blocked until PLL is locked
Strapping pins or SMBus for configuration;
3.3V tolerant SMBus interface support
Very low jitter outputs
Differential cycle-to-cycle jitter <50ps
Differential output-to-output skew <50ps
ÎÎPCIe Gen1/Gen2/Gen3 compliant
Packaging (Pb-free & Green): 32-lead 5×5mm TQFN