PI4MSD5V9545A数据手册集成电路（IC）的信号开关多路复用器解码器规格书PDF

描述 Description

The PI4MSD5V9545A is a quad 1-of-4 bidirectional translating switch, controlled via the I2C/SMBus. The SCL/SDA upstream pair fans out to four SCx/SDx downstream pairs, or channels.Any individual SCx/SDx channel or combination of channels can be selected, determined by the contents of the programmable control register. Four interrupt inputs, INT0 to INT3, one for each of the downstream pairs, are provided. One interrupt output, INT, acts as an AND of the four interrupt inputs. An active LOW reset input allows the PI4MSD5V- 9545A/45B/45C to recover from a situation where one of the downstream buses is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C/SMBus state machine and causes all the channels to be deselected as does the internal power-on reset function.The pass gates of the switches are constructed such that the VCC pin can be used to limit the maximum high voltage which will be passed by the PI4MSD5V9545A/45B/45C. This allows the use of different bus voltages on each pair, so that 1.2V, 1.8V or 2.5V or 3.3V parts can communicate with 5V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5V tolerant. The PI4MSD5V9545A , PI4MSD5V9545B and PI4MSD5V9545C are identical except for the fixed portion of the slave address.

特性 Features

1-of-4 bidirectional translating multiplexer
I2C-bus interface logic; compatible with SMBus standards
Operating power supply voltage range of 1.65V to 5.5V
Allows voltage level translation between 1.2V, 1.8V, 2.5V, 3.3V and 5V buses
Low standby current
Low Ron switches
Channel selection via I2C-bus
Power-up with all multiplexer channels deselected
No glitch on power-up
Supports hot insertion
5V tolerant inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000V HBM per JESD22-A114, and 1000V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: SOIC (S20), TSSOP (L20)