DSP Embedded Line and Port Interface Controller

Addendum to “DELIC Clock System Synchronization” The DELIC Clock System Synchronization is described in the DELIC-LC PEB 20570/DELIC-PB PEB 20571 Data Sheet, independent of the version (2.1 .. 3.1). As an addendum to chapter “DELIC Clock System Synchronization” of the DELICLC/DELIC-PB Data Sheet

文件：170.77 Kbytes 页数：8 Pages

Infineon

英飞凌

S/T Bus Interface Circuit (SBC)

The S-Bus Interface Circuit (SBC) PEx 2080 implements the four-wire S/T-interface used to link voice/data terminals to an ISDN. Through selection of operating mode, the device may be employed in all types of applications involving an S interface. Two or more SBC´s can be used to build a point to-p

文件：1.74272 Mbytes 页数：73 Pages

SIEMENS

西门子

Smart Integrated Digital Echo Canceller

Introduction The Smart Integrated Digital Echo Canceller (SIDEC) suppresses echoes in telecommunication networks which might disturb any kind of terrestrial or wireless communication. It incorporates leading edge CMOS technology as well as INFINEON’s many years experience in Telecommunication ICs

文件：2.46758 Mbytes 页数：164 Pages

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RF Power Plate Capacitors for Higher Voltages Class 1 Ceramic

• Low losses • High reliability • High voltage ratings

文件：104.35 Kbytes 页数：7 Pages

VishayVishay Siliconix

威世威世科技公司

Quad E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

Abstract This document is an Addendumto the PEF 22554 HT/E, QuadFALC®, Version 2.1 Data Sheet DS1, release date 2002-09. It describes data that has to be changed or added.

文件：914.89 Kbytes 页数：30 Pages

Infineon

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Quad E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

Abstract This document is an Addendumto the PEF 22554 HT/E, QuadFALC®, Version 2.1 Data Sheet DS1, release date 2002-09. It describes data that has to be changed or added.

文件：914.89 Kbytes 页数：30 Pages

Infineon

英飞凌

Quad E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

Abstract This document is an Addendumto the PEF 22554 HT/E, QuadFALC®, Version 2.1 Data Sheet DS1, release date 2002-09. It describes data that has to be changed or added.

文件：914.89 Kbytes 页数：30 Pages

Infineon

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E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications

Introduction The FALC®56 framer and line interface component is designed to fulfill all required interfacing between analog E1/T1/J1 lines and the digital PCM system highway, H.100/H.110 or H-MVIP bus for world market telecommunication systems. Features Line Interface • High-density, generic i

文件：6.4204 Mbytes 页数：518 Pages

Infineon

英飞凌

E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications

Introduction The FALC®56 framer and line interface component is designed to fulfill all required interfacing between analog E1/T1/J1 lines and the digital PCM system highway, H.100/H.110 or H-MVIP bus for world market telecommunication systems. Features Line Interface • High-density, generic i

文件：6.4204 Mbytes 页数：518 Pages

Infineon

英飞凌

E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications

Introduction The FALC®56 framer and line interface component is designed to fulfill all required interfacing between analog E1/T1/J1 lines and the digital PCM system highway, H.100/H.110 or H-MVIP bus for world market telecommunication systems. Features Line Interface • High-density, generic i

文件：6.4204 Mbytes 页数：518 Pages

Infineon

英飞凌