PEB24902中文资料西门子数据手册PDF规格书

Overview

The PEB 24902 Quad IEC AFE (Quadruple ISDN Echocancellation Circuit Analogue Front End) is part of a 2B1Q or 4B3T ISDN U-transceiver chip set. Up to four lines can be accessed simultaneously by the Quad IEC AFE. The Quad IEC AFE is optimized to work in conjunction with the PEB 24901 Quad IEC DFE-T and the PEB 24911 Quad IEC DFE-Q. An integrated PLL synchronizes the 15.36 MHz Master clock onto the 8 kHz or 2048 kHz PTT Clock. This specification describes the functionality for 2B1Q and 4B3T interfaces.

Features

• Digital to Analogue conversion (transmit pulse)

• Output buffering

• Analogue to digital conversion

• Detection of signal on the line

• Master clock generation by PLL

• P-MQFP-64 Package

• Compliant to ANSI T1.601 (1992), ETSI ETR 080 (1995)

• JTAG boundary scan path compliant to IEEE 1149.1