PE99D Series 3.3 V PECL Clock Oscillators

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PLETRONICS

Dual N-Channel Enhancement-Mode Vertical DMOS FET

General Description This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input i

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SUTEX

Dual N-Channel Enhancement-Mode Vertical DMOS FETs

Low Threshold DMOS Technology These dual low threshold enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertexs wellproven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with

文件：81.29 Kbytes 页数：4 Pages

SUTEX

Dual N-Channel Enhancement-Mode Vertical DMOS FETs

Low Threshold DMOS Technology These dual low threshold enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertexs wellproven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with

文件：81.29 Kbytes 页数：4 Pages

SUTEX