16 X 12 BIT COMPLEX MULTIPLIER

The PDSP16112/PDSP16112A will multply a complex (16+16) bit word by a complex (12+12) bit coefficient word and produce a complex (17+17) bit rounded product. FEATURES ■ 20MHz Complex Number (16+16) x (12+12) Multplication ■ Pipeline Architecture ■ Power Dissipation only 500mW ■ TTL Compatible

文件：456.92 Kbytes 页数：9 Pages

ZARLINK

Zarlink Semiconductor Inc

Stand Alone FFT Processor

The PDSP16515A performs Forward or Inverse Fast Fourier Transforms on complex or real data sets containing up to 1024 points. Data and coefficient input are both represented by 16 bits. Data is expanded internally to 18 bits and subject to Block Floating Point arithmetic to preserve a greater dyna

文件：173.73 Kbytes 页数：25 Pages

ZARLINK

Zarlink Semiconductor Inc

Stand Alone FFT Processor

The PDSP16510 performs Forward or Inverse Fast Fourier Transforms on complex or real data sets containing up to 1024 points. Data and coefficients are each represented by 16 bits, with block floating point arithmetic for increased dynamic range. FEATURES ■ Completely self contained FFT Processor

文件：181.05 Kbytes 页数：23 Pages

ZARLINK

Zarlink Semiconductor Inc

32K BUCKET BUFFER

The PDSP16540 Bucket Buffer is for use in systems which require a reservoir in which a block of data is accumulated, whilst previous data is being transferred to other system elements and then processed. It thus prevents the loss of incoming data whilst the previous block is being processed. Like

文件：316.8 Kbytes 页数：11 Pages

ZARLINK

Zarlink Semiconductor Inc

Complex Accumulator

The PDSP16318 contains two independent 20-bit Adder/Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 10MHz throughout in FFT and filter applications. Two PDSP16318s combined with a single PDSP16112A Complex Multiplier provide a complete

文件：91.56 Kbytes 页数：7 Pages

ZARLINK

Zarlink Semiconductor Inc

16 by 16 Bit Complex Multiplier

The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional twos complement. FEATURES ■ Complex Number (16 + 16) X (16 + 16) Multiplication ■ Full 32 bit Re

文件：149.08 Kbytes 页数：18 Pages

ZARLINK

Zarlink Semiconductor Inc

ALU and Barrel Shifter

文件：121.12 Kbytes 页数：16 Pages

ZARLINK

Zarlink Semiconductor Inc

ALU and Barrel Shifter

文件：171.76 Kbytes 页数：18 Pages

MITEL

Complex Accumulator

文件：137.62 Kbytes 页数：8 Pages

MITEL

Pythagoras Processor

文件：150.36 Kbytes 页数：12 Pages

MITEL