PDSP16256GC1R

The PDSP16318/A contains two independent 20-bit Adder/Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 20MHz throughout in FFT and filter applications. Two PDSP16318As combined with a single PDSP16112A Complex Multiplier provide a compl

文件：88.7 Kbytes 页数：8 Pages

MITEL

16 by 16 Bit Complex Multiplier

The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional twos complement. FEATURES ■ Complex Number (16 + 16) X (16 + 16) Multiplication ■ Full 32 bit Re

文件：149.08 Kbytes 页数：18 Pages

ZARLINK

Zarlink Semiconductor Inc

Complex Accumulator

The PDSP16318 contains two independent 20-bit Adder/Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 10MHz throughout in FFT and filter applications. Two PDSP16318s combined with a single PDSP16112A Complex Multiplier provide a complete

文件：91.56 Kbytes 页数：7 Pages

ZARLINK

Zarlink Semiconductor Inc

Complex Accumulator

文件：137.62 Kbytes 页数：8 Pages

MITEL