16 by 16 Bit Complex Multiplier

The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional twos complement. FEATURES ■ Complex Number (16 + 16) X (16 + 16) Multiplication ■ Full 32 bit Re

文件：149.08 Kbytes 页数：18 Pages

ZARLINK

Zarlink Semiconductor Inc

16 by 16 Bit Complex Multiplier

The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional twos complement. FEATURES ■ Complex Number (16 + 16) X (16 + 16) Multiplication ■ Full 32 bit Re

文件：149.08 Kbytes 页数：18 Pages

ZARLINK

Zarlink Semiconductor Inc

16 by 16 Bit Complex Multiplier

The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional twos complement. FEATURES ■ Complex Number (16 + 16) X (16 + 16) Multiplication ■ Full 32 bit Re

文件：149.08 Kbytes 页数：18 Pages

ZARLINK

Zarlink Semiconductor Inc

16 X 16 Bit Complex Multiplier

The PDSP16116 contains four 16316 array multipliers, two 32-bit adder/subtractors and all the control logic required to support Block Floating Point Arithmetic as used in FFT applications. The PDSP16116A variant will multiply two complex (16116) bit words every 50ns and can be configured to outpu

文件：270.66 Kbytes 页数：17 Pages

MITEL