PCK2010RADL数据手册恩XP中文资料规格书

描述 Description

OverviewThe PCK2010RA is a clock generator (frequency synthesizer) chip for a Pentium II and other similar processors.
The PCK2010RA has four CPU clock outputs at 2.5 V, two CPUDIV2 clock outputs running at ½ CPU clock frequency (66 MHz or 50 MHz depending on the state of SEL133/100) and four 3V66 clocks running at 66MHz. There are eight PCI clock outputs running at 33 MHz. One of the PCI clock outputs is free-running. Additionally, the part has three 2.5 V IOAPIC clock outputs at 16.67 MHz and two 3.3 V reference clock outputs at 14.318 MHz. All clock outputs meet Intel?s drive strength, rise/fall time, jitter, accuracy, and skew requirements.
The part possesses dedicated power-down, CPUSTOP, and PCISTOP input pins for power management control. These inputs are synchronized on-chip and ensure glitch-free output transitions. When the CPUSTOP input is asserted, the CPU clock outputs and 3V66 clock outputs are driven LOW. When the PCISTOP input is asserted, the PCI clock outputs are driven LOW.
Finally, when the PWRDWN input pin is asserted, the internal reference oscillator and PLLs are shut down, and all outputs are driven LOW.

特性 Features

•Mixed 2.5 V and 3.3 V operation

•Four CPU clocks at 2.5 V

•Eight PCI clocks at 3.3 V, one free-running (synchronous with CPU clocks)

•Four 3.3 V fixed clocks @ 66 MHz

•Two 2.5 V CPUDIV2 clocks @ ² CPU clock frequency

•Three 2.5 V IOAPIC clocks @ 16.67 MHz

•One 3.3 V 48 MHz USB clock

•Two 3.3 V reference clocks @ 14.318 MHz

•Reference 14.31818 MHz Xtal oscillator input

•133 MHz or 100 MHz operation, 133.01 MHz in 133 mode

•Power management control input pins

•CPU clock jitter max. 250 ps cycle-cycle

•CPU clock skew max. 175 ps pin-pin

•0.0 ns - 1.5 ns CPU-3V66 delay

•1.5 ns - 3.5 ns 3V66-PCI delay

•1.5 ns - 4.0 ns CPU-IOAPIC delay

•1.5 ns - 4.0 ns CPU-PCI delay

•Available in 56-pin SSOP package

•+- 0.6 pct. center spread spectrum capability via select pins

•-0.6 pct. down spread spectrum capability via select pins