PCI2250数据手册集成电路（IC）的专用规格书PDF

描述 Description

The Texas Instruments PCI2250 PCI-to-PCI bridge provides a high performance connection path between two peripheral component interconnect (PCI) buses. Transactions occur between masters on one PCI bus and targets on another PCI bus, and the PCI2250 allows bridged transactions to occur concurrently on both buses. The bridge supports burst-mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act independently. The PCI2250 bridge is compliant with the PCI Local Bus Specification, and can be used to overcome the electrical loading limits of 10 devices per PCI bus and one PCI device per expansion slot by creating hierarchical buses. The PCI2250 provides two-tier internal arbitration for up to four secondary bus masters and may be implemented with an external secondary PCI bus arbiter. The PCI2250 provides compact-PCI (CPCI) hot-swap extended capability, which makes it an ideal solution for multifunction compact-PCI cards and adapting single function cards to hot-swap compliance. The PCI2250 bridge is compliant with the PCI-to-PCI Bridge Specification. It can be configured for positive decoding or subtractive decoding on the primary interface, and provides several additional decode options that make it an ideal bridge to custom PCI applications. Two extension windows are included, and the PCI2250 provides decoding of serial and parallel port addresses. The PCI2250 is compliant with PCI Power Management Interface Specification Revisions 1.0 and 1.1. Also, the PCI2250 offers PCI CLKRUN bridging support for low-power mobile and docking applications. The PCI2250 has been designed to lead the industry in power conservation. An advanced CMOS process is utilized to achieve low system power consumption while operating at PCI clock rates up to 33 MHz.

特性 Features

• Configurable for PCI Power Management Interface Specification Revision 1.0 or 1.1 support
• Compact-PCI friendly silicon as defined in the Compact-PCI Hot Swap Specification
• 3.3-V core logic with universal PCI interface compatible with 3.3-V and 5-V PCI signaling environments
• Two 32-bit, 33-MHz PCI buses
• Provides internal two-tier arbitration for up to four secondary bus masters and supports an external secondary bus arbiter
• Burst data transfers with pipeline architecture to maximize data throughput in both directions
• Provides programmable extension windows and port decode options
• Independent read and write buffers for each direction
• Provides five secondary PCI clock outputs
• Predictable latency per PCI Local Bus Specification
• Propagates bus locking
• Secondary bus is driven low during reset
• Provides VGA palette memory and I/O, and subtractive decoding options
• Advanced submicron, low-power CMOS technology
• Fully compliant with PCI-to-PCI Bridge Architecture Specification
• Packaged in 160-pin QFP (PCM) and 176-pin thin QFP (PGF)