PCD5093中文资料飞利浦数据手册PDF规格书

GENERAL DESCRIPTION

The PCD5093 is designed as GAP-compliant basestation chip for ISDN or n lines (PCD5096) business systems. It has an embedded 80C51 microcontroller with twice the performance of the classic architecture, 64 kbytes of PROM program memory and 3 kbytes of data memory on chip. In addition there is 1 kbyte of on-chip data memory that is shared with on-chip Burst Mode Logic (BML) and DSP, the System Data RAM (SDR).

FEATURES

• 80C51 ports P0, P1, P2 and P3 available for interfacing to display, keyboard, I2C-bus, interrupt sources and/or external memory. Integrated 64 kbyte ROM, 3 kbytes of data memory and 1 kbyte SDR-RAM. External program memory is addressable up to 128 kbytes

• +2.7 to +5 V port (P0 to P3) interface

• TDMA frame (de)multiplexing. Transmission or reception can be programmed for any slot

• Ciphering, scrambling, CRC checking/generation and protected B-fields

• Speech and data buffering space for six handsets

• Local call and B-field loop-back

• Two interrupt lines for BML and DSP to interrupt 80C51

• On-chip, three-channel time-multiplexed 8-bit Analog-to-Digital Converter (ADC) for RSSI measurement, one for battery voltage measurement and one channel available for other purposes

• On-chip 8-bit Digital-to-Analog Converter (DAC) for electronic potentiometer function

• Phase error measurement and phase error correction by hardware

• DACs and ADCs for dynamic earpiece and dynamic or electret microphone

• On-chip reference voltage

• On-chip supply for electret microphone

• Very low ohmic buzzer output

• Serial interface to external ADPCM CODEC (PCD5032) or 8 kHz u-law samples

• Speech switch for Digital Telephone Answering Machine (DTAM) connected to SPI interface

• IOM-2 interface (Siemens registered trademark)

• Serial interface to synthesizer for frequency programming

• Programmable polarity and timing of radio-control signals

• GMSK pulse shaper

• Easy interfacing with radio circuits, operating at other supply voltages (RF supply pin with level shifter for RF signals)

• On-chip comparator for use as data-slicer

• Low power oscillator with integrated frequency adjustment

• QFP100 package

• Power-on-reset

• Low supply voltage (2.7 to 3.6 V)

• CMOS technology.