首页>PCD5002H>规格书详情

PCD5002H数据手册恩XP中文资料规格书

PDF无图
厂商型号

PCD5002H

功能描述

Advanced POCSAG and APOC-1 Paging Decoder

制造商

恩XP 恩XP

中文名称

N智浦

数据手册

下载地址下载地址二

更新时间

2025-8-6 22:50:00

人工找货

PCD5002H价格和库存,欢迎联系客服免费人工找货

PCD5002H规格书详情

描述 Description

GENERAL DESCRIPTION
The PCD5002 is a very low power pager decoder and controller, capable of handling both standard POCSAG and the advanced APOC-1 code. Continuous data decoding upon reception of a dedicated sync word is available for news pager applications.
Data rates supported are 512, 1200 and 2400 bits/s using a single 76.8 kHz crystal. On-chip EEPROM is programmable using a minimum supply voltage of 2.0 V, allowing ‘over-the-air’ programming. I2C-bus compatible.FEATURES
• Wide operating supply voltage range: 1.5 to 6.0 V
• EEPROM programming requires only 2.0 V supply
• Low operating current: 50 µA typ. (ON), 25 µA typ. (OFF)
• Temperature range −25 to +70 °C
• “CCIR radio paging Code No. 1” (POCSAG) compatible
• Supports Advanced Pager Operator’s Code Phase 1 (APOC-1) for extended battery economy
• 512, 1200 and 2400 bits/s data rates using 76.8 kHz crystal
• Built-in data filter (16-times oversampling) and bit clock recovery
• Advanced ACCESS synchronization algorithm
• 2-bit random and (optional) 4-bit burst error correction
• Up to 6 user addresses (RICs), each with 4 functions/alert cadences
• Up to 6 user address frames, independently programmable
• Standard POCSAG sync word, plus up to 4 user programmable sync words
• Continuous data decoding upon reception of user programmable sync word (optional)
• Received data inversion (optional)
• Call alert via beeper, vibrator or LED
• 2-level acoustic alert using single external transistor
• Alert control: automatic (POCSAG type), via cadence register or alert input pin
• Separate power control of receiver and RF oscillator for battery economy
• Synthesizer set-up and control interface (3-line serial)
• On-chip EEPROM for storage of user addresses (RICs), pager configuration and synthesizer data
• On-chip SRAM buffer for message data
• Slave I2C-bus interface to microcontroller for transfer of message data, status/control and EEPROM programming (data transfer at up to 100 kbits/s)
• Wake-up interrupt for microcontroller, programmable polarity
• Direct and I2C-bus control of operating status (ON/OFF)
• Battery-low indication (external detector)
• Out-of-range condition indication
• Real time clock reference output
• On-chip voltage doubler
• Interfaces directly to UAA2080 and UAA2082 paging receivers.APPLICATIONS
• Advanced display pagers (POCSAG and APOC-1)
• Basic alert-only pagers
• Information services
• Personal organizers
• Telepoint
• Telemetry/data transmission.

特性 Features

• Wide operating supply voltage range: 1.5 to 6.0 V
• EEPROM programming requires only 2.0 V supply
• Low operating current: 50 µA typ. (ON), 25 µA typ. (OFF)
• Temperature range −25 to +70 °C
• “CCIR radio paging Code No. 1” (POCSAG) compatible
• Supports Advanced Pager Operator’s Code Phase 1 (APOC-1) for extended battery economy
• 512, 1200 and 2400 bits/s data rates using 76.8 kHz crystal
• Built-in data filter (16-times oversampling) and bit clock recovery
• Advanced ACCESS synchronization algorithm
• 2-bit random and (optional) 4-bit burst error correction
• Up to 6 user addresses (RICs), each with 4 functions/alert cadences
• Up to 6 user address frames, independently programmable
• Standard POCSAG sync word, plus up to 4 user programmable sync words
• Continuous data decoding upon reception of user programmable sync word (optional)
• Received data inversion (optional)
• Call alert via beeper, vibrator or LED
• 2-level acoustic alert using single external transistor
• Alert control: automatic (POCSAG type), via cadence register or alert input pin
• Separate power control of receiver and RF oscillator for battery economy
• Synthesizer set-up and control interface (3-line serial)
• On-chip EEPROM for storage of user addresses (RICs), pager configuration and synthesizer data
• On-chip SRAM buffer for message data
• Slave I2C-bus interface to microcontroller for transfer of message data, status/control and EEPROM programming (data transfer at up to 100 kbits/s)
• Wake-up interrupt for microcontroller, programmable polarity
• Direct and I2C-bus control of operating status (ON/OFF)
• Battery-low indication (external detector)
• Out-of-range condition indication
• Real time clock reference output
• On-chip voltage doubler
• Interfaces directly to UAA2080 and UAA2082 paging receivers.

技术参数

  • 型号:

    PCD5002H

  • 功能描述:

    Telecommunication Decoder

供应商 型号 品牌 批号 封装 库存 备注 价格
PHI
23+
QFP
20000
全新原装假一赔十
询价
PHI
24+
QFP
80000
只做自己库存 全新原装进口正品假一赔百 可开13%增
询价
PHI
00+
QFP32
880000
明嘉莱只做原装正品现货
询价
PHI
25+
QFP-32
65428
百分百原装现货 实单必成
询价
PHI
2000
QFP
6000
一级代理,专注军工、汽车、医疗、工业、新能源、电力
询价
PHILIP
17+
QFP
9700
只做全新进口原装,现货库存
询价
PHI
24+
QFP
12000
原装正品 有挂就有货
询价
PHI
1836+
QFP32
9852
只做原装正品现货!或订货假一赔十!
询价
PHI
20+
TQFP32
500
样品可出,优势库存欢迎实单
询价
PHI
1996
QFP
368
原装现货海量库存欢迎咨询
询价